Author(s) Details:
Chaitanya Kommu
Department of EEC, GITAM University, Visakhapatnam, AP, India.
A Daisy Rani
Department of Instrument Technology, Andhra University, Visakhapatnam, AP, India.
This section is a part of the chapter: Presenting the Design of Low-Power High-Speed Two-Level Three input XOR Gate
The Static CMOS logic implementation of digital integrated arithmetic circuits offers low static power and best choice for power efficiency, it also observes a high propagation delay compared it its counterparts (Balobas, Konofaos (2017). The construction of pull-up and pull-down networks of static realization actually leads to low power constraints. The pull-up network drags the output to a logic high value whereas the pull-down network pulls down the output node to a logic low level. The general construction of static CMOS is shown in Fig. 1(a) (Kommu and Rani (2020). In general, pMOS FETs for the Pull-up network and nMOS FETs for the pull-down network are used. For example, the static CMOS NAND and NOR gate are shown in Fig. 1(b) and Fig. 1(c) respectively. This implementation promises very low static power since at a time only one network is active to obtain the output signal and good noise margin but requires more transistors if the fan in of the digital circuit increases. It is possible to reduce the number of transistors by taking two-level realization of large fans in circuits. It is noticed that the input capacitance and propagation delay of the circuit will increase.
How to Cite
Kommu, C., & Rani, A. D. (2025). Presenting the Design of Low-Power High-Speed Two-Level Three input XOR Gate. Science and Technology: Developments and Applications Vol. 5, 1–14. https://doi.org/10.9734/bpi/stda/v5/2365