The Development of Embedded Packages without Interconnects : A Part from The Book Chapter : Quasi-3D Thermal Modelling of Advanced Electronic Systems in Package

Interconnects

The chip stacking technology became an available option to increase the effective performance of the packaging systems. 2D package mounts two or more dies in a single plane on the package substrate. In a 2.5D package, an interposer between the die and the package substrate is added. It is an electrical interface that reroutes the signal from one connection to several different connections. Furthermore, the thin silicon interposer (about 100 microns) with high thermal conductivity λSi = 140 W/(m∙K) promotes the better internal heat dissipation. 3D package stacks the dies in the vertical dimension.

Author(s) Details:

Konstantin O. Petrosyants,
National Research University Higher School of Economics (Moscow Institute of Electronics and Mathematics), Moscow, Russia and Institute for Design Problems in Microelectronics, Russian Academy of Sciences, Moscow, Russia.

Nikita I. Ryabov,
National Research University Higher School of Economics (Moscow Institute of Electronics and Mathematics), Moscow, Russia.

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